Method and system for handling multiple 3-d video formats

ABSTRACT

Aspects of a method and system for handling multiple 3-D video formats are provided. A video processing system may receive one or more video frames comprising first 3-D view pixel data and second 3-D view pixel data suitable for generating a three-dimensional (3-D) video frame. The video system may be operable to determine an arrangement of the first 3-D view pixel data and the second view pixel data in the one or more video frames. In instances that the determined arrangement is not a desired arrangement, the video processing system may be operable to convert the one or more video frames to the desired arrangement. Either or both of the determined arrangement and the desired arrangement may comprise a series of two single-view frames. Either or both of the determined arrangement and the desired arrangement may comprise a single frame comprising the first 3-D view pixel data and the second 3-D view pixel data.

CLAIM OF PRIORITY

This patent application makes reference to, claims priority to andclaims benefit from:

U.S. Provisional Patent Application Ser. No. 61/296,851 (Attorney DocketNo. 22866US01) filed on Jan. 20, 2010;U.S. Provisional Patent Application Ser. No. 61/267,729 (Attorney DocketNo. 20428US01) filed on Dec. 8, 2009; andU.S. Provisional Patent Application Ser. No. 61/330,456 (Attorney DocketNo. 23028US01) filed on May 3, 2010.

Each of the above stated applications is hereby incorporated herein byreference in its entirety.

INCORPORATION BY REFERENCE

This patent application also makes reference to:

U.S. Provisional patent application Ser. No. ______ (Attorney Docket No.23437US02) filed on Dec. 8, 2010;U.S. Provisional patent application Ser. No. ______ (Attorney Docket No.23438US02) filed on Dec. 8, 2010;U.S. Provisional patent application Ser. No. ______ (Attorney Docket No.23439US02) filed on Dec. 8, 2010; andU.S. Provisional patent application Ser. No. ______ (Attorney Docket No.23440US02) filed on Dec. 8, 2010.

Each of the above stated applications is hereby incorporated herein byreference in its entirety.

FIELD OF THE INVENTION

Certain embodiments of the invention relate to video processing. Morespecifically, certain embodiments of the invention relate to a methodand system for handling multiple 3-D video formats.

BACKGROUND OF THE INVENTION

Support of three-dimensional (3-D) video presents many complexities thatare not addressed in conventional two-dimensional (2D) video processingsystems. The rapid growth of 3-D video systems has resulted ininconsistent and inadequate ways of dealing with these complexities.

Further limitations and disadvantages of conventional and traditionalapproaches will become apparent to one of skill in the art, throughcomparison of such systems with some aspects of the present invention asset forth in the remainder of the present application with reference tothe drawings.

BRIEF SUMMARY OF THE INVENTION

A system and/or method is provided for handling multiple 3-D videoformats, substantially as illustrated by and/or described in connectionwith at least one of the figures, as set forth more completely in theclaims.

These and other advantages, aspects and novel features of the presentinvention, as well as details of an illustrated embodiment thereof, willbe more fully understood from the following description and drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is diagram illustrating a video processing system, in accordancewith an embodiment of the invention.

FIG. 2 is flow chart illustrating exemplary operation for convertingbetween arrangements of 3-D pixel data, in accordance with an embodimentof the invention.

FIG. 3 is a diagram illustrating various arrangements of one or moreframes comprising 3-D pixel data, in accordance with an embodiment ofthe invention.

FIG. 4A is a diagram illustrating reception and storage of asingle-frame-left-right arrangement of 3-D pixel data, in accordancewith an embodiment of the invention.

FIG. 4B is a diagram illustrating reception and storage of asingle-frame-over-under arrangement of 3-D pixel data, in accordancewith an embodiment of the invention.

FIG. 4C is a diagram illustrating reception and storage of atwo-frame-sequential arrangement of 3-D pixel data, in accordance withan embodiment of the invention.

FIG. 5A is a diagram illustrating reading 3-D pixel data from memory togenerate a left-right-single-frame arrangement of 3-D pixel data, inaccordance with an embodiment of the invention.

FIG. 5B is a diagram illustrating reading 3-D pixel data from memory togenerate an over-under-single-frame arrangement of 3-D pixel data, inaccordance with an embodiment of the invention.

FIG. 5C is a diagram illustrating reading 3-D pixel data from memory togenerate a multi-frame arrangement of 3-D pixel data, in accordance withan embodiment of the invention.

FIG. 6 is a flow chart illustrating exemplary steps for 3-D videoprocessing, in accordance with an embodiment of the invention.

DETAILED DESCRIPTION OF THE INVENTION

Various embodiments of the invention may be found in a method and systemfor handling multiple 3-D video formats. In various embodiments of theinvention, a video processing system may receive one or more videoframes comprising pixel data for a first 3-D view and pixel data for asecond 3-D view, which may both be suitable for generating athree-dimensional (3-D) video frame. The pixel data for the first 3-Dview via may be referred to as the first 3-D view pixel data and thepixel data for the second 3-D view via may be referred to as the second3-D view pixel data. The video system may be operable to determine anarrangement of the first 3-D view pixel data and the second 3-D viewpixel data in the one or more video frames. In instances that thedetermined arrangement is not a desired arrangement, the videoprocessing system may be operable to convert the one or more videoframes to the desired arrangement. Either one or both of the determinedarrangement and the desired arrangement may comprise a series of twosingle-view frames, and each of the single-view frames may comprise oneof the first 3-D view pixel data and the second 3-D view pixel data.Either or both of the determined arrangement and the desired arrangementmay comprise a single frame comprising the first 3-D view pixel data andthe second 3-D view pixel data. The single frame may be arranged suchthat a left portion of the single frame comprises the first 3-D viewpixel data and a right portion of the single frame comprises the second3-D view pixel data. The single frame may be arranged such that a topportion of the single frame comprises the first 3-D view pixel data anda bottom portion of the single frame comprises the second 3-D view pixeldata. The single frame may be arranged such that the first 3-D viewpixel data is interleaved with the second 3-D view pixel data.

The converting may comprise writing the first 3-D view pixel data to oneor more locations in memory identified by a first one or more pointersand/or writing the second 3-D view pixel data to one or more locationsin memory identified by a second one or more pointers. The convertingmay also comprise reading the first 3-D view pixel data and the second3-D view pixel data from memory in an order that is different than anorder in which the first 3-D view pixel data and the second 3-D viewpixel data was written to memory. The video system may receive the first3-D view pixel data and second 3-D view pixel data via a first switchingelement that is operable to convey pixel data onto one or more of aplurality of data paths, and via a second switching element that isoperable to convey pixel data from the plurality of data paths tomemory, to the first switching element, and to a compositor. Which oneor more of the data paths the left-view pixel data and the right-viewpixel data is conveyed onto may be based on the determined arrangementand the desired arrangement. As utilized herein a “3-D view” refers toone view (i.e., a left view or a right view) of a stereoscopic image,“3-D pixel data” refers to pixel data of one or both views of astereoscopic image, and 3-D video refers to stereoscopic video.

FIG. 1 is diagram illustrating a video processing system, in accordancewith an embodiment of the invention. Referring to FIG. 1, the videoprocessing system 100 comprises video input interface 106, video feeder108, MPEG feeder 110, multiplexers 112 a and 112 b, processing paths 114₁-114 _(J), bypass paths 116 ₁-116 _(K), loopback paths 118 ₁-118 _(L),capture module 120, compositor 122, memory 124, and the memory 126. Eachof J, K, and L is an integer greater than or equal to 1. In variousembodiments of the invention, the system 100 may, for example, reside ina set-top box, a television, or a desktop or laptop computer. In anexemplary embodiment of the invention, the system 100 may be implementedin single semiconductor die or “chip.” A chip may comprise, for example,an ASIC or an FPGA. In an exemplary embodiment of the invention, theportion of the system 100 enclosed in the dashed line comprise asingle-chip video processor.

Each of the memory 124, and the memory 126 may comprise RAM, ROM, NVRAM,flash, a hard drive, or any other suitable memory device. The memory124, and memory 126 may be physically distinct memory elements of may bedifferent portions and/or partitions of a single memory device.

The video input interface 106 may comprise suitable logic, circuitry,interfaces, and/or code that may be operable to receive a video streamand convey the pixel data of the video stream to the multiplexer 112 a.The video input interface 106 may comprise, for example, a VGAinterface, composite video interface, component video interface, HDMIinterface, DisplayPort interface, and/or other suitable interface andthe video stream into the interface 106 may be formatted accordingly.The received video stream may comprise monoscopic (2-D) video dataand/or stereoscopic (3-D) video data. While this application focuses onprocessing of received 3-D video streams. Exemplary details ofprocessing 2-D video streams are described in U.S. patent applicationSer. No. ______ (Attorney Docket No. 23438US02) and in U.S. patentapplication Ser. No. ______ (Attorney Docket No. 23439US02) each ofwhich is incorporated by reference above.

The video feeder 108 may comprise suitable logic, circuitry, interfaces,and/or code that may be operable to input pixel data corresponding tolocally generated graphics to the multiplexer 112 a. In this regard, thevideo feeder 108 may, for example, read pixel data out of the memory 126and convey the pixel data to the multiplexer 112 a.

The MPEG feeder 110 may comprise suitable logic, circuitry, interfaces,and/or code that may be operable to receive an MPEG stream and processthe MPEG stream to output pixel data to the multiplexer 112 a. In thisregard, the MPEG stream may be received via a networking device (notshown).

Each of the multiplexers 112 a and 112 b may comprise suitable logic,circuitry, interfaces, and/or code that may be operable to route pixeldata between any one or more inputs of the multiplexer to any one ormore outputs of the multiplexer. Pixel data input to the multiplexer 112a from any one of more of the interface 106, feeder 108, and the feeder110 may be conveyed to any one or more of the processing paths 114 ₁-114_(J) and/or any one or more of the bypass paths 116 ₁-116 _(K). Each ofthe processing paths 114 ₁-114 _(J) may comprise suitable logic,circuitry, interfaces, and/or code that may be operable to perform oneor more processing functions. Exemplary processing functions comprisescaling, subsampling, deinterlacing, blur/sharpen, color adjustment, andnoise reduction. Each of the bypass paths 116 ₁-116 _(K) may enablepixel data to be conveyed unchanged from the multiplexer 112 a to themultiplexer 112 b. Each of the loopback paths 118 ₁-118 _(L) may enablepixel data to be conveyed from the multiplexer 112 b to the multiplexer112 a. In this manner, the loopback paths may, for example, enableprocessing the same pixel data via multiple ones of the processing paths114 ₁-114 _(J).

The capture module 120 may comprise suitable logic, circuitry,interfaces, and/or code that may be operable to write 3-D pixel data tothe memory 126. The capture module 120 may be operable to write first3-D view pixel data to the memory 126 utilizing a first one or morememory pointers. The capture module 120 may be operable to write second3-D view pixel data to the memory 126 utilizing a second one or morememory pointers. First 3-D view pixel data may be left-view data, andsecond 3-D view pixel data may be right-view pixel data, or visa-versa.For example, left-view pixel data may be captured via a left lens of avideo camera and right-view pixel data may be captured via a right lensof the video camera.

The compositor 122 may comprise suitable logic, circuitry, interfaces,and/or code that may be operable to generate an output video streamwhich may be output via, for example, a VGA output, composite videooutput, component video output, HDMI output, and/or DisplayPort output.The output video stream may comprise pixel data received from themultiplexer 112 b and/or pixel data read from memory 124. In thisregard, the compositor 122 may be operable to concurrently present pixeldata from the memory 124 and pixel data from the multiplexer 112 b. Forexample, graphics from the memory 124 may be overlaid on the pixel datafrom the multiplexer 112 b. The output video stream may comprisemonoscopic (2-D) video data and/or stereoscopic (3-D) video data. Whilethis application focuses on outputting 3-D video streams. Exemplarydetails of processing 2-D video streams are described in U.S. patentapplication Ser. No. ______ (Attorney Docket No. 23438US02) and in U.S.patent application Ser. No. ______ (Attorney Docket No. 23439US02) eachof which is incorporated by reference above.

In operation, one or more 3-D video frames may be input to the system100 via one or more of the interface 106, the feeder 108, and the feeder110. Each of the one or more input frames may comprise live-actionimages and/or computer-generated images. The input frame(s) may compriseleft-view pixel data and right-view pixel data. The arrangement of theinput frame(s) may correspond to any one of the arrangements describedbelow with respect to FIG. 3. The arrangement of the input frame(s) maybe determined in any of a variety of ways. For example, the system 100may determine the arrangement of the input frame(s) based on the sourcefrom which the one or more frames was received, based on a state of oneor more control signals in the system 100, and/or based on inspectionthe input frame(s).

The multiplexer 112 a may convey the received frame(s) to themultiplexer 112 b via one or more of the processing paths 114 ₁-114 _(J)and/or one or more of the bypass paths 116 ₁-116 _(K). In this regard,the frame(s) may make multiple passes from the multiplexer 112 a to themultiplexer 112 b and thus may traverse one or more of the loopbackpaths 118 ₁-118 _(L).

Upon arriving at the multiplexer 112 b, after one or more traversals ofone or more of the processing paths 114 ₁-114 _(J), bypass paths 116₁-116 _(K), and/or loopback paths 118 ₁-118 _(L), the frame(s) may beconveyed to the capture module 120. The capture module 120 may write theleft-view pixel data and right-view pixel data to the memory 126. Theleft-view pixel data may be written to one or more memory locationsidentified by a first one or more pointers. The right-view pixel datamay be written to one or more memory locations identified by a secondone or more pointers.

Subsequently, the feeder module 108 may read the left-view andright-view pixel data from the memory 126 to generate one or more outputframes. The first one or more pointers and the second one or morepointers may be utilized for reading the pixel data out from the memory126. The order in which the pixel data is read from memory may depend onthe arrangement of the input frame(s) and the desired arrangement of theoutput frame(s). In this regard, the arrangement of the output frameread from the memory 126 may correspond to any of the arrangementsdescribed below with respect to FIG. 3. Thus, in instances that thearrangement of the input frame(s) is the same as the arrangement of theoutput frame(s), the pixel data may be read out of the memory 126 in thesame order in which it was written to the memory 126. Conversely, ininstances that the arrangement of the input frame(s) is the differentthan the arrangement of the output frame(s), the pixel data may be readout of the memory 126 in a different order than which it was written tothe memory 126.

The output frame(s) may be conveyed to the compositor 122. In someinstances, prior to being conveyed to the compositor 122, the outputframe(s) may be conveyed to the multiplexer 112 a for one or moretraversals of one or more of the processing paths 114 ₁-114 _(J), bypasspaths 116 ₁-116 _(K), and/or loopback paths 118 ₁-118 _(L).

The compositor 122 may process the output frame(s) to make the outputframe(s) suitable for insertion into a video stream. The video streammay be formatted so as to be compatible with one or more video standardssuch as VGA, composite video, component video, HDMI, and/or DisplayPort.Processing of the output frame(s) may comprise combining the outputframe(s) from the multiplexer 112 b with pixel data from memory 124. Forexample, graphics may be read from the memory 124 and overlaid on theoutput frame(s) from the multiplexer 112 b.

FIG. 2 is flow chart illustrating exemplary operation for convertingbetween arrangements of 3-D pixel data, in accordance with an embodimentof the invention. Referring to FIG. 2, the exemplary steps begin withstep 202 in which an input frame is conveyed to the multiplexer 112 a.

In step 204, it is determined whether the input frame(s) are to traverseone or more of the processing paths 114 ₁-114 _(J) or traverse one ormore of the bypass paths 116 ₁-116 _(K). In instances that the inputframe(s) are to traverse one or more of the processing paths 114 ₁-114_(J), then in step 224, processing, such as scaling and/ordeinterlacing, may occur.

In step 206, the input frame(s) are conveyed to the multiplexer 112 b.In step 208 it is determined whether the input frame(s) are to belooped-back to multiplexer 112 a for another traversal of one or more ofthe processing paths processing paths 114 ₁-114 _(J) and/or one or moreof the bypass paths 116 ₁-116 _(K). In instances that the input frame(s)are to be looped-back, the exemplary steps may return to step 202. Ininstances that the input frame(s) are not to be looped-back, theexemplary steps may advance to step 210.

In step 210, the input frame(s) are captured to the memory 126. Thefirst 3-D pixel data of the input frame(s) may be stored to memorylocation(s) indicated by a first one or more memory pointers. The second3-D view pixel data of the input frame(s) may be stored to memorylocation(s) indicated by a second one or more memory pointers.

In step 212, the left-view pixel data and right-view pixel data is readfrom the memory 126 to generate one or more output frame(s). The orderin which the data is read from the memory 126 may depend on the desiredarrangement of the output frame(s).

In step 214, it is determined whether the output frame(s) are beprocessed by one or more of the processing paths 114 ₁-114 _(J). Ininstances that the output frame(s) are to be processed, then theexemplary steps may advance to step 226.

In step 226, the output frame(s) are communicated to the multiplexer 112a. In step 228, the output frame(s) are conveyed onto one or more of theprocessing paths 114 ₁-114 _(J) for processing, such as scaling and/ornoise reduction. In step 230, the output frame(s) may arrive at themultiplexer 112 b. In step 232 it may be determined whether the outputframe(s) are to be looped-back to multiplexer 112 a for anothertraversal of one or more of the processing paths processing paths 114₁-114 _(J) and/or one or more of the bypass paths 116 ₁-116 _(K). Ininstances that the output frame(s) are to be looped-back, the exemplarysteps may return to step 226. In instances that the output frame(s) arenot to be looped-back, the exemplary steps may advance to step 216.

In step 216, the output frame(s) arrive at the multiplexer 112 b. Instep 218 the output frame(s) are conveyed to the compositor 122. In step220, the compositor may process the output frame(s) to make themsuitable for insertion into a video stream. Processing the outputframe(s) may comprise combining the output frame(s) from the multiplexer112 b with pixel data from memory 124. For example, graphics may be readfrom the memory 124 and overlaid on the output frame(s) from themultiplexer 112 b.

In step 222, the video stream may be communicated to another videodevice, such as a television or monitor. The video stream may, forexample, be formatted in accordance with one or more video standardssuch as VGA, composite video, component video, HDMI, and/or DisplayPort.

FIG. 3 is a diagram illustrating various arrangements of one or moreframes comprising 3-D pixel data, in accordance with an embodiment ofthe invention. Referring to FIG. 3, there is shown atwo-frame-sequential arrangement 302, a left-right-single-framearrangement 304, an over-under-single-frame arrangement 306, avertically-interleaved-single-frame arrangement 308, ahorizontally-interleaved-single-frame arrangement 310, and avertically-and-horizontally-interleaved-single-frame arrangement 312.For the following description of the various arrangements, each of N andM may be any positive integer.

The two-frame-sequential arrangement 302 comprises a first framecomprising first 3-D view pixel data and a second frame comprisingsecond 3-D view pixel data. The two frames may be received by the system100 sequentially. That is, the first frame may be received earlier intime before the second frame.

The left portion of the left-right-single-frame arrangement 304 maycomprise first 3-D view pixel data and the right portion of theleft-right single-frame arrangement 304 may comprise second 3-D viewpixel data. An exemplary 4M×4N left-right-single-frame arrangement isdescribed in table 1 below.

TABLE 1 Left-Right-Single-Frame arrangement Col. 1-2M Col. 2M + 1-4MLines 1-4N first 3-D view second 3-D view

The top portion of the over-under-single-frame arrangement 306 maycomprise first 3-D view pixel data and the bottom portion of theover-under-single-frame arrangement 306 may comprise second 3-D viewpixel data. An exemplary 4M×4N over-under-single-frame arrangement isdescribed in table 2 below.

TABLE 2 Over-Under-Single-Frame Arrangement Col. 1-4M Lines 1-2N first3-D view Lines 2N + 1-4N second 3-D view

The vertically-interleaved-single-frame arrangement 308 may alternatebetween one or more lines of left-view pixel data and one or more linesof right-view pixel data. An exemplary 4M×4Nvertically-interleaved-single-frame arrangement is described in table 3below.

TABLE 3 Vertically-Interleaved-Single-Frame Arrangement Col. 1-4M Lines1-N first 3-D view Lines N + 1-2N second 3-D view Lines 2N + 1-3N first3-D view Lines 3N + 1-4N second 3-D view

The horizontally-interleaved-single-frame arrangement 310 may alternatebetween one or more columns of left-view pixel data and one or morecolumns of right-view pixel data. An exemplary 4M×4Nhorizontally-interleaved-single-frame arrangement is described in table4 below.

TABLE 4 Horizontally-Interleaved-Single-Frame Arrangement Col. M + Col.2M + Col. 3M + Col. 1-M 1-2M 1-3M 1-4M Lines 1-4N first 3-D view secondfirst 3-D view second 3-D view 3-D view

In the vertically-and-horizontally-interleaved-single-frame arrangement312, the first 3-D view and second 3-D view pixel data may beinterleaved in both a vertical and horizontal direction. An exemplary4M×4N horizontally-interleaved-single-frame arrangement is described intable 4 below.

TABLE 5 Vertically-and-Horizontally-Interleaved-Single-Frame ArrangementCol. 1-M Col. M + 1-2M Col. 2M + 1-3M Col. 3M + 1-4M Lines 1-N first 3-Dview second 3-D view first 3-D view second 3-D view Lines N + 1-2Nsecond 3-D view first 3-D view second 3-D view first 3-D view Lines 2N +1-3N first 3-D view second 3-D view first 3-D view second 3-D view Lines3N + 1-4N second 3-D view first 3-D view second 3-D view first 3-D view

FIG. 4A is a diagram illustrating reception and storage of asingle-frame-left-right arrangement of 3-D pixel data, in accordancewith an embodiment of the invention. Referring to FIG. 4A, there isshown a 4×2 left-right-single-frame arrangement 402 being written to thememory 126. The pixel data may be written to the memory 126 in the orderin which it was received. In this regard, the pixel data may be receivedline by line with each line being received from left to right. That is,pixel data may arrive in the following order: column 1 line 1, column 2line 1, column 3 line 1, column 4 line 1, column 1 line 2, column 2,line 2, column 3, line 3, column 4 line 4. First 3-D view pixel data maybe written to the location(s) 150 a of the memory 126 and second 3-Dview pixel data may be written to the location(s) 150 b of the memory126. The location(s) 150 a may be identified by a first one or morememory pointers and the location(s) 150 b may be identified by a secondone or more memory pointers. Although the first 3-D view pixel data andsecond 3-D view pixel data are depicted as being written to the samememory, the invention is not so restricted. For example, first 3-D viewpixel data may be written to a first memory and second 3-D view pixeldata may be written to a second memory.

FIG. 4B is a diagram illustrating reception and storage of asingle-frame-over-under arrangement of 3-D pixel data, in accordancewith an embodiment of the invention. Referring to FIG. 4B, there isshown a 2×4 over-under-single-frame arrangement 406 being written to thememory 126. The pixel data may be written to the memory 126 in the orderin which it was received. In this regard, the pixel data may be receivedline by line, with each line being received from left to right. That is,pixel data may arrive in the following order: column 1 line 1, column 2line 1, column 1 line 2, column 2 line 2, column 1 line 3, column 2,line 3, column 1, line 4, column 2 line 4. First 3-D view pixel data maybe written to the location(s) 150 a of the memory 126 and second 3-Dview pixel data may be written to the location(s) 150 b of the memory126. The location(s) 150 a may be identified by a first one or morememory pointers and the location(s) 150 b may be identified by a secondone or more memory pointers. Although the first 3-D view pixel data andsecond 3-D view pixel data are depicted as being written to the samememory, the invention is not so restricted. For example, first 3-D viewpixel data may be written to a first memory and second 3-D view pixeldata may be written to a second memory.

FIG. 4C is a diagram illustrating reception and storage of atwo-frame-sequential arrangement of 3-D pixel data, in accordance withan embodiment of the invention. Referring to FIG. 4C, there is shown a2×2 frame 408 a comprising first 3-D view pixel data and 2×2 frame 408 bcomprising second 3-D view pixel data being written to the memory 126.The pixel data may be written to the memory 126 in the order in which itwas received. In this regard, frame 408 a may be received before frame408 b. Each frame may be received line by line, with each line beingreceived from left to right. That is, pixel data may arrive in thefollowing order: column 1 line 1 of frame 408 a, column 2 line 1 offrame 408 a, column 1 line 2 of frame 408 a, column 2 line 2 of frame408 a, column 1 line 1 of frame 408 b, column 2 line 1 of frame 408 b,column 1 line 2 of frame 408 b, and column 2 line 2 of frame 408 b.First 3-D view pixel data may be written to the location(s) 150 a of thememory 126 and second 3-D view pixel data may be written to thelocation(s) 150 b of the memory 126. The location(s) 150 a may beidentified by a first one or more memory pointers and the location(s)150 b may be identified by a second one or more memory pointers.Although the first 3-D view pixel data and second 3-D view pixel dataare depicted as being written to the same memory, the invention is notso restricted. For example, first 3-D view pixel data may be written toa first memory and second 3-D view pixel data may be written to a secondmemory.

FIG. 5A is a diagram illustrating reading 3-D pixel data from memory togenerate a left-right-single-frame arrangement of 3-D pixel data, inaccordance with an embodiment of the invention. Referring to FIG. 5A,there is shown a 4×2 left-right-single-frame arrangement 502 being readfrom the memory 126. The pixel data may be read from memory line byline, with each line being read from left to right. That is, pixel datamay be read in the following order: first 3-D view pixel data may beread out for column 1 line 1 and column 2 line 1, second 3-D view pixeldata may be read out for column 3 line 1 and column 4 line 1, first 3-Dview pixel data may be read out for column 1 line 2 and column 2, line2, and second view pixel data may be read out for column 3, line 3 andcolumn 4 line 4.

FIG. 5B is a diagram illustrating reading 3-D pixel data from memory togenerate an over-under-single-frame arrangement of 3-D pixel data, inaccordance with an embodiment of the invention. Referring to FIG. 5B,there is shown a 2×4 over-under-single-frame arrangement 506 being readfrom the memory 126. The pixel data may be read from memory line byline, with each line being read from left to right. That is, pixel datamay be read in the following order: first 3-D view pixel data may beread out for column 1 line 1, then column 2 line 1, then column 1 line2, then column 2 line 2. Second 3-D view pixel data may then be read outfor column 1 line 3, then column 2, line 3, then column 1, line 4, thencolumn 2 line 4.

FIG. 5C is a diagram illustrating reading 3-D pixel data from memory togenerate a two-frame-sequential arrangement of 3-D pixel data, inaccordance with an embodiment of the invention. Referring to FIG. 5C,there is shown 2×2 frames 508 a and 508 b being read from the memory126. The pixel data may be read from memory line by line, with each linebeing read from left to right. That is, pixel data may be read in thefollowing order: first 3-D view pixel data may be read out for column 1line 1 of frame 508 a, then column 2 line 1 of frame 508 a, then column2 line 1 of frame 508 a, then column 2 line 2 of frame 508 a.Subsequently, second 3-D view pixel data may be read out for column 1line 1 of frame 508 b, then column 2 line 1 of frame 508 b, then column2 line 1 of frame 508 b, then column 2 line 2 of frame 508 b.

FIG. 6 is a flow chart illustrating exemplary steps for 3-D videoprocessing, in accordance with an embodiment of the invention. Referringto FIG. 6, after start step 602, the system 100 may be configured toselect an output frame arrangement. The output frame arrangement may beselected based on, for example, the device(s) from which the system 100receives a video stream and/or the device(s) to which the system 100outputs a video stream. In step 606, the system 100 may receive one ormore frames comprising 3-D pixel data. The arrangement of the inputframe(s) may be any of the arrangements described with respect to FIG.3. In step 608, the system 100 may determine the arrangement of theinput frame(s). This determination may be based on, for example, aninspection of the input frame(s), the source from which the frame(s)were received, and/or based on a pre-configuration of the system 100. Instep 610, the input frame(s) may be processed, if necessary. Theprocessing may comprise, for example, scaling, de-interlacing, noisereduction, and/or chroma subsampling. In step 612, the pixel data of theinput frame(s) may be stored to memory, with first 3-D view pixel databeing stored to one or more locations identified by a first one or morepointers and second 3-D view pixel data being stored to one or morelocations identified by a second one or more pointers. In step 614, thepixel data may be read from memory to generate one or more outputframes. The arrangement of the output frame(s) may be any of thearrangements described with respect to FIG. 3. In step 616, the outputframe(s) may be processed, if necessary. The processing may comprise,for example, scaling, de-interlacing, noise reduction, and/or chromasubsampling. In step 618, the output frame may be processed forinsertion into a video stream, and inserted into the video stream. Thevideo stream may be communicated to, for example, a television ormonitor.

Various aspects of the invention may be found in a method and system forhandling multiple 3-D video formats. In an exemplary embodiment of theinvention, a video processing system 100 may receive one or more videoframes, such one or more of the frames 402, 406, 408 a and 408 b,comprising first 3-D view pixel data and second 3-D view pixel datasuitable for generating a three-dimensional (3-D) video frame. The videosystem 100 may be operable to determine an arrangement of the first 3-Dview pixel data and the second view pixel data in the one or more videoframes, where the arrangement corresponds to one of the arrangements302-312. In instances that the determined arrangement is not a desiredarrangement, the video processing system 100 may be operable to convertthe one or more video frames to the desired arrangement. Either or bothof the determined arrangement and the desired arrangement may be thearrangement 302 and may comprise a series of two single-view frames,each of the single-view frames comprising one of the first 3-D viewpixel data and the second 3-D view pixel data.

Either or both of the determined arrangement and the desired arrangementmay be one of the arrangements 304-312 and comprise a single framecomprising the first 3-D view pixel data and the second 3-D view pixeldata. The single frame may be arranged as arrangement 304 and a leftportion of the single frame may comprise the first 3-D view pixel dataand a right portion of the single frame may comprise the second 3-D viewpixel data. The single frame may be arranged as arrangement 306 and atop portion of the single frame may comprise the first 3-D view pixeldata and a bottom portion of the single frame may comprise the second3-D view pixel data. The single frame may be arranged as one ofarrangements 308, 310, and 312 and may comprise the first 3-D view pixeldata interleaved with the second 3-D view pixel data.

The converting may comprise writing the first 3-D view pixel data to oneor more locations 150 a in the memory 126 identified by a first one ormore pointers. The converting may comprise writing the second 3-D viewpixel data to one or more locations 150 b in the memory 126 identifiedby a second one or more pointers. The converting may comprise readingthe first 3-D view pixel data and the second 3-D view pixel data frommemory in an order that is different than an order in which the first3-D view pixel data and the second 3-D view pixel data was written tomemory. The video processing system 100 may receive the first 3-D viewpixel data and second 3-D view pixel data via a first switching element112 a that is operable to convey pixel data onto one or more of aplurality of data paths 114 ₁-114 _(J) and/or 116 ₁-116 _(K), and via asecond switching element 112 b that is operable to convey pixel datafrom the plurality of data paths 114 ₁-114 _(J) and/or 116 ₁-116 _(K) tothe memory 126 (via capture module 120), to the first switching element112 a, and to the compositor 122. Which one or more of the data paths114 ₁-114 _(J), 116 ₁-116 _(K) and/or 118 ₁-118 _(L) and/or theleft-view pixel data and the right-view pixel data is conveyed onto maybe based on the determined arrangement and the desired arrangement.

Other embodiments of the invention may provide a non-transitory computerreadable medium and/or storage medium, and/or a non-transitory machinereadable medium and/or storage medium, having stored thereon, a machinecode and/or a computer program having at least one code sectionexecutable by a machine and/or a computer, thereby causing the machineand/or computer to perform the steps as described herein for handlingmultiple 3-D video formats.

Accordingly, the present invention may be realized in hardware,software, or a combination of hardware and software. The presentinvention may be realized in a centralized fashion in at least onecomputer system, or in a distributed fashion where different elementsare spread across several interconnected computer systems. Any kind ofcomputer system or other apparatus adapted for carrying out the methodsdescribed herein is suited. A typical combination of hardware andsoftware may be a general-purpose computer system with a computerprogram that, when being loaded and executed, controls the computersystem such that it carries out the methods described herein.

The present invention may also be embedded in a computer programproduct, which comprises all the features enabling the implementation ofthe methods described herein, and which when loaded in a computer systemis able to carry out these methods. Computer program in the presentcontext means any expression, in any language, code or notation, of aset of instructions intended to cause a system having an informationprocessing capability to perform a particular function either directlyor after either or both of the following: a) conversion to anotherlanguage, code or notation; b) reproduction in a different materialform.

While the present invention has been described with reference to certainembodiments, it will be understood by those skilled in the art thatvarious changes may be made and equivalents may be substituted withoutdeparting from the scope of the present invention. In addition, manymodifications may be made to adapt a particular situation or material tothe teachings of the present invention without departing from its scope.Therefore, it is intended that the present invention not be limited tothe particular embodiment disclosed, but that the present invention willinclude all embodiments falling within the scope of the appended claims.

1. A method comprising: in a video processing device: receiving one ormore video frames, said received one or more frames comprising first 3-Dview pixel data and second 3-D view pixel data for generating athree-dimensional (3-D) video frame; determining an arrangement of saidfirst 3-D view pixel data and said second 3-D view pixel data in saidone or more video frames; and in instances that said determinedarrangement is not a desired arrangement, converting said one or morevideo frames to said desired arrangement.
 2. The method of claim 1,wherein: one of said determined arrangement and said desired arrangementcomprises a series of two single-view frames, each of said single-viewframes comprising one of said first 3-D view pixel data and said second3-D view pixel data; and one of said determined arrangement and saiddesired arrangement comprises a single frame, said single framecomprising said first 3-D view pixel data and said second 3-D view pixeldata.
 3. The method of claim 2, wherein said single frame is arrangedsuch that a left portion of said single frame comprises said first 3-Dview pixel data and a right portion of said single frame comprises saidsecond 3-D view pixel data.
 4. The method of claim 2, wherein saidsingle frame is arranged such that a top portion of said single framecomprises said first 3-D view pixel data and a bottom portion of saidsingle frame comprises said second 3-D view pixel data.
 5. The method ofclaim 1, wherein: one of said determined arrangement and said desiredarrangement comprises a left-right single frame, a left portion of saidleft-right single frame comprising said first 3-D view pixel data and aright portion of said left-right single frame comprising said second 3-Dview pixel data; and one of said determined arrangement and said desiredarrangement comprises an over-under single frame, a top portion of saidover-under single frame comprising said first 3-D view pixel data and abottom portion of said over-under single frame comprising said second3-D view pixel data.
 6. The method of claim 1, wherein: one of saiddetermined arrangement and said desired arrangement comprises aninterleaved single frame, said interleaved single frame comprising saidfirst 3-D view pixel data interleaved with said second 3-D view pixeldata; and one of said determined arrangement and said desiredarrangement comprises a left-right single frame, a left portion of saidleft-right single frame comprising said first 3-D view pixel data and aright portion of said left-right single frame comprising said second 3-Dview pixel data.
 7. The method of claim 1, wherein: one of saiddetermined arrangement and said desired arrangement corresponds to aninterleaved single frame, said interleaved single frame comprising saidfirst 3-D view pixel data interleaved with said second 3-D view pixeldata; and one of said determined arrangement and said desiredarrangement corresponds to a over-under single frame, a top portion ofsaid over-under single frame comprising said first 3-D view pixel dataand a bottom portion of said over-under single frame comprises saidsecond 3-D view pixel data.
 8. The method of claim 1: wherein saidconverting comprises: writing said first 3-D view pixel data to one ormore locations in memory identified by a first one or more pointers;writing said second 3-D view pixel data to one or more locations inmemory identified by a second one or more pointers; and reading saidfirst 3-D view pixel data and said second 3-D view pixel data frommemory in an order that is different than an order in which said first3-D view pixel data and said second 3-D view pixel data was written tomemory.
 9. The method according to claim 1, comprising receiving saidfirst 3-D view pixel data and second 3-D view pixel data via: a firstswitching element that is operable to convey pixel data onto one or moreof a plurality of data paths; and a second switching element that isoperable to convey pixel data from said plurality of data paths tomemory, to said first switching element, and to a compositor.
 10. Themethod according to claim 9, comprising selecting which one or more ofsaid data paths onto which said pixel data for 3-D left view and saidpixel data 3-D right view is conveyed based on said determinedarrangement and said desired arrangement.
 11. A system comprising: oneor more circuits for use in a video processing system, said one or morecircuits being operable to: receive one or more video frames, said oneor more frames comprising first 3-D view pixel data and second 3-D viewpixel data suitable for generating a three-dimensional (3-D) videoframe; determine an arrangement of said first 3-D view pixel data andsaid second view pixel data in said one or more video frames; and ininstances that said determined arrangement is not a desired arrangement,convert said one or more video frames to said desired arrangement. 12.The system of claim 11, wherein: one of said determined arrangement andsaid desired arrangement comprises a series of two single-view frames,each of said single-view frames comprising one of said first 3-D viewpixel data and said second 3-D view pixel data; and one of saiddetermined arrangement and said desired arrangement comprises a singleframe, said single frame comprising said first 3-D view pixel data andsaid second 3-D view pixel data.
 13. The system of claim 12, whereinsaid single frame is arranged such that a left portion of said singleframe comprises said first 3-D view pixel data and a right portion ofsaid single frame comprises said second 3-D view pixel data.
 14. Thesystem of claim 12, wherein said single frame is arranged such that atop portion of said single frame comprises said first 3-D view pixeldata and a bottom portion of said single frame comprises said second 3-Dview pixel data.
 15. The system of claim 11, wherein: one of saiddetermined arrangement and said desired arrangement comprises aleft-right single frame, a left portion of said left-right single framecomprising said first 3-D view pixel data and a right portion of saidleft-right single frame comprising said second 3-D view pixel data; andone of said determined arrangement and said desired arrangementcomprises an over-under single frame, a top portion of said over-undersingle frame comprising said first 3-D view pixel data and a bottomportion of said over-under single frame comprising said second 3-D viewpixel data.
 16. The system of claim 11, wherein: one of said determinedarrangement and said desired arrangement comprises an interleaved singleframe, said interleaved single frame comprising said first 3-D viewpixel data interleaved with said second 3-D view pixel data; and one ofsaid determined arrangement and said desired arrangement comprises aleft-right single frame, a left portion of said left-right single framecomprising said first 3-D view pixel data and a right portion of saidleft-right single frame comprising said second 3-D view pixel data. 17.The system of claim 11, wherein: one of said determined arrangement andsaid desired arrangement corresponds to an interleaved single frame,said interleaved single frame comprising said first 3-D view pixel datainterleaved with said second 3-D view pixel data; and one of saiddetermined arrangement and said desired arrangement corresponds to aover-under single frame, a top portion of said over-under single framecomprising said first 3-D view pixel data and a bottom portion of saidover-under single frame comprises said second 3-D view pixel data. 18.The system of claim 11: wherein said converting comprises: writing saidfirst 3-D view pixel data to one or more locations in memory identifiedby a first one or more pointers; writing said second 3-D view pixel datato one or more locations in memory identified by a second one or morepointers; reading said first 3-D view pixel data and said second 3-Dview pixel data from memory in an order that is different than an orderin which said first 3-D view pixel data and said second 3-D view pixeldata was written to memory.
 19. The system according to claim 11,wherein said one or more circuits are operable to receive said first 3-Dview pixel data and second 3-D view pixel data via: a first switchingelement that is operable to convey pixel data onto one or more of aplurality of data paths; a second switching element that is operable toconvey pixel data from said plurality of data paths to: memory, to saidfirst switching element, and to a compositor.
 20. The system accordingto claim 19, wherein said one or more circuits are operable to selectwhich one or more of said data paths onto which said left-view pixeldata and said right-view pixel data is conveyed based on said determinedarrangement and said desired arrangement.